1. Field of the Invention
The present invention relates to a multiphase clock divider, and more particularly, to a multiphase clock divider that can be designed according to timing margin requirements by generating reference clocks.
2. Description of the Prior Art
As integrated circuit systems become more complex, system requirements for clock stability and accuracy also become higher. A multiphase clock divider capable of simultaneously generating one or more clocks having a same frequency but different phases is widely utilized in various systems such as data transmission systems in a wired or wireless network, or microprocessor systems.
Please refer to FIG. 1A, which is a schematic diagram of a conventional multiphase clock divider 100. The multiphase clock divider 100 receives N input clocks Sin and generates N divide-by-k output clocks Sout. As shown in FIG. 1A, if frequency of the input clocks Sin is fo, frequency of the output clocks Sout will be fo/k, wherein the N input clocks Sin have N different phases, and the N output clocks Sout also have N different phases respectively corresponding to the phases of the N input clocks Sin.
Most systems, however, can only operate with a small number of clocks; hence, another multiphase clock divider has N input clocks corresponding to one output clock. Please refer to FIG. 1B, which is a schematic diagram of a conventional multiphase clock divider 102. The multiphase clock divider 102 receives N input clocks Sin and generates one divide-by-k output clock Sout. As shown in FIG. 1B, if frequency of the input clocks Sin is fo, frequency of the output clock Sout will be fo/k, wherein the N input clocks Sin have N different phases, and the output clock Sout may have N*k different kinds of phases. If the system requires more than one output clock, the structure in FIG. 1B can be duplicated to generate output clocks with a plurality of different phases.
A clock divider can be realized by utilizing a divide-by-2 clock dividing circuit. Please refer to FIG. 2A and FIG. 2B, where FIG. 2A illustrates a divide-by-2 clock divider 20 realized by utilizing a D flip-flop, and FIG. 2B is a waveform diagram of an input clock Sin and an output clock Sout of the divide-by-2 clock divider 20. As shown in FIG. 2B, when the input clock Sin is switched from a lower voltage level to a higher voltage level, the output clock Sout may be switched from a lower voltage level to a higher voltage level or from a higher voltage level to a lower voltage level. There are two kinds of different phase relationships between the input clock Sin and the output clock Sout. When the divisor of the clock divider increases, there may be more than two kinds of phase relationships between the input clock Sin and the output clock Sout. For example, when T divide-by-2 clock dividers are connected in series, a divide-by-2T clock divider can be achieved, and the output clock and the input clock of the divide-by-2T clock divider may possess 2T kinds of different phase relationships.
A conventional method for calibrating phase of an output clock is detect-and-reset. For a divide-by-2T clock divider, each divide-by-2 clock divider may have an individual detecting circuit, and each detecting circuit utilizes three input clocks with different phases to determine which phase the output clock of each divide-by-2 clock divider has, so as to determine whether to perform a reset. For example, please refer to FIG. 3A, which is a schematic diagram of a conventional detect-and-reset multiphase clock divider 30. The multiphase clock divider 30 generates N output clocks PHO(360°*i/N), wherein i can be any positive integer between 1 and N. As shown in FIG. 3A, for each input clock PHI(360°*i/N) and the corresponding output clock PHO(360°*i/N), the multiphase clock divider 30 needs to utilize input clocks PHI(360°*i/N), PHI(360°*(i+1)/N), and PHI(360°*(i+2)/N) to perform detect-and-reset. Please refer to FIG. 3B, which takes a divide-by-4 clock divider 310 as an example, where the divide-by-4 clock divider 310 includes divide-by-2 circuits 312, 314 and detect-and-reset control circuits 316, 318. As shown in FIG. 3B, an input clock PHI(0°) is divided by the divide-by-2 circuit 312 to generate a medium clock PHM(0°), and the medium clock PHM(0°) is further divided by the divide-by-2 circuit 314 to generate an output clock PHO(0°). The medium clock PHM(0°) and the input clock PHI(0°) may possess two kinds of phase relationships; hence, the detect-and-reset control circuit 316 has to utilize three input clocks with different phases PHI(0°), PHI(360°*1/N), and PHI(360°*2/N) to determine which phase the medium clock PHM(0°) has, so as to determine whether to perform a reset. The output clock PHO(0°) and the medium clock PHM(0°) may also possess two kinds of phase relationships; hence, the detect-and-reset control circuit 318 has to utilize three medium clocks with different phases PHM(0°), PHM(360°*1/N), and PHM(360°*2/N) to determine which phase the output clock PHO(0°) has, so as to determine whether to perform a reset.
The medium clocks PHM(360°*1/N) and PHM(360°*2/N) must be further generated by utilizing PHI(360°*1/N) and PHI(360°*2/N) via different divide-by-2 clock dividers, respectively. Therefore, other input clocks and detect-and-reset control circuits are required for ensuring phases of the medium clocks PHM(360°*1/N) and PHM(360°*2/N) are accurate. As a result, when the divisor of the clock divider increases, even if only one output clock is required, the required input clocks and control circuits may still increase significantly. In addition, the detect-and-reset control circuits 316, 318 must utilize double the input frequency for detection, such that an operational speed of the system may be reduced.
The industry has further developed a delay type multiphase clock divider. Please refer to FIG. 4, which is a schematic diagram of a conventional delay type multiphase clock divider 40. As shown in FIG. 4, an output clock of each stage is a delay version of an output clock of the previous stage, where there is a fixed phase relationship between two adjacent output clocks. Since the highest frequency of the control signals in the delay type multiphase clock divider 40 is the same as the input frequency, operational speed of the delay type multiphase clock divider 40 may be higher than the detect-and-reset multiphase clock divider 30. Set-up time of the delay type multiphase clock divider 40, however, is fo/N, wherein fo is frequency of the input clock and N is the number of phases. When N becomes greater, the set-up time will fall accordingly, which may limit the operational speed of the system.